![]() ![]() Moreover, the integration also provides 2.22× energy efficiency compared with the superscalar processor along. The vector program with software-level optimizations achieves 9.53× improvement on instruction throughput and 10.18× improvement on real-time throughput. The forward propagation of a convolution neural network model is evaluated by the standalone superscalar processor and the integration of the vector co-processor. Compared to the reference work, the proposed design improves 18.9% on average instruction throughput and 4.92% on average prediction hit rate, with 16.9% higher operating clock frequency synthesized on the Intel Arria 10 FPGA board. According to the definition of the proposed vector instruction set, the scratchpad memory and element-wise arithmetic units are implemented in the vector co-processor.ĭifferent test programs are evaluated on the fully-tested superscalar processor. The superscalar processor is extended with a customized vector instruction set of single-instruction-multiple-data computations to specifically improve the performance on machine learning tasks. Data flow in the instruction dispatch and commit stages is optimized to achieve higher instruction throughput. The processor is capable of speculative execution with five checkpoints. ![]() The proposed design employs the global sharing scheme for branch prediction and Tomasulo algorithm for out-of-order execution. ![]() This thesis presents a dual-issue superscalar RISC-V processor design with dynamic execution. RISC-V processors are becoming popular in many fields of applications and research. The demand is convened by the stable and extensible open-sourced RISC-V instruction set architecture. 122-128, 2016.With the increasing number of digital products in the market, the need for robust and highly configurable processors rises. Index Terms-Branch target buffer, superscalar processor, FPGA.Īuthors are with the Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan (e-mail: Meng, Kosaku Fukuda, Takeshi Kumaki, and Takeshi Ogura, "An Optimal CAM-based Separated BTB for a Superscalar Processor," International Journal of Computer Theory and Engineering vol. A super-scalar processor is one that is capable of sustaining an instruction-execution rate of more than one. The experiment results show that proposed BTB improved IPC about 3.12% by adding an optimum of 128 entries to the current BTB with a CAM structure, and the optimal replacement algorithm is the rotation method. A superscalar processor uses register renaming and out-of-order execution techniques to detect and enhance the amount of instruction-level parallelism between instructions so that it can execute multiple instructions per clock cycle. Superscalar processor design defines a set of approaches that enable the central processing unit (CPU) of a computer to obtain a throughput of higher than one instruction per cycle while implementing an individual sequential program. We equip our BTB on FPGA to measure the hardware size and use SimpleScalar to measure the performance. In contrast to a scalar processor that can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction. For the replacement algorithms of CAM, we test a least recently used method and a rotation method. From Wiki - Superscalar processor: (Line 1): superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. One is static random access memory (SRAM) and the other is content addressable memory (CAM). For optimization the separated BTB, we test NBTB by using two kinds of memory structures. The CBTB uses the current BTB, and the NBTB is added on the current BTB. ![]() This paper proposes a novel BTB that separates current BTB into conditional branch BTB (CBTB) and non-conditional branch BTB (NBTB). Hence, increasing the accuracy of BTB prediction has become more important. Summary From Scalar to Superscalar Processors In the previous chapter we introduced a five-stage pipeline. Assume registers are read at the issue stage and branch resolution happens. However, BTB misprediction increases penalty by using deeper pipelines and larger windows in a current processor. Assume a superscalar processor has the following pipeline stages: F D I X0 X1 W. Abstract-Branch target buffer (BTB) is an important component for predicting branch target addresses to improve the performance of superscalar processor. ![]()
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